Hardware Design Engineering, Director - OEM, Silicon Validation Platforms & Rack-Scale Design - Taiwan

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are hiring a Director of Hardware Design Engineering — OEM, Silicon Validation Platforms & Rack-Scale Design to establish and lead Astera Labs' Taiwan hardware engineering center. This role serves as the primary hardware engineering hub for OEM customer engagement across Asia, while simultaneously owning the design and development of Silicon Validation Platforms (SVB/EVB) and rack-scale products (AI chassis, switch trays, CEM cards).

This is a high-impact leadership role that combines three critical functions:

• OEM Design Enablement & Customer Support — Serving as the front-line hardware engineering partner for OEM customers in Asia (hyperscale cloud, server/switch OEMs, cable/module manufacturers) who are integrating Astera Labs silicon into their own products

• Silicon Validation Platform Design (SVB/EVB) — Designing and delivering the evaluation boards and system validation platforms that enable silicon bring-up, characterization, customer evaluation, and reference design seeding

• Rack-Scale Product Design — Designing AI chassis-class systems, switch trays, CEM cards, and system-level hardware that showcase Astera Labs' full connectivity portfolio

You will build and lead a multidisciplinary hardware engineering team in Taiwan — spanning electrical/PCB design, mechanical engineering, validation, and customer applications engineering. You'll serve as the senior Astera Labs hardware engineering leader in Asia, partnering with OEM customers, ODM partners, and contract manufacturers while maintaining tight alignment with the Santa Clara-based engineering organization.

Reporting to the Senior Director of Hardware Design Engineering, you'll operate with significant autonomy while ensuring strategic alignment on technology roadmap, design standards, and customer priorities.

Key Responsibilities

• Taiwan Engineering Center Leadership

• Establish, build, and lead Astera Labs' Taiwan hardware engineering center as the company's primary Asia-based hub for OEM engagement, silicon platform design, and rack-scale product development

• Recruit, hire, and develop a high-caliber multidisciplinary engineering team in Taiwan, including:

• Hardware/PCB design engineers

• Mechanical engineers

• Validation engineers

• Customer/applications hardware engineers

• Lab engineers

• Define organizational structure, hiring roadmap, and operating model for the Taiwan center — balancing local autonomy with global alignment

• Establish lab infrastructure in Taiwan to support silicon platform bring-up, customer demonstrations, OEM design reviews, interoperability testing, and rack-scale system validation

• Drive engineering culture that emphasizes customer responsiveness, design excellence, and tight collaboration with Santa Clara headquarters

• Serve as the senior Astera Labs engineering leader in Asia — representing the company with customers, partners, and industry stakeholders in the region

• OEM Design Enablement & Customer Engagement

• Customer Design Support:

• Serve as the primary hardware engineering interface for OEM customers in Asia who are designing Astera Labs silicon (retimers, re-drivers, connectivity ASICs) into their own products

• Provide expert-level design review support for customer hardware designs — reviewing schematics, PCB layouts, stackups, power delivery networks, thermal solutions, and signal integrity

• Deliver hands-on technical engagement during customer design cycles — from initial architecture consultation through prototype bring-up, debug, and production readiness

• Support customer hardware debug and troubleshooting when integration challenges arise — coordinating across internal teams (silicon, firmware, SI, validation) to provide rapid root-cause analysis and corrective guidance

• Travel to customer sites across Asia (Taiwan, China, Japan, Korea) to provide on-site design review, bring-up support, and integration assistance for critical programs

• Reference Design & Design Collateral Development:

• Develop and maintain production-quality reference designs for Astera Labs silicon — including reference schematics, recommended PCB layouts, stackup guidelines, power delivery reference circuits, and thermal design examples

• Create comprehensive hardware design guides, integration manuals, application notes, and best-practice documentation that enable OEM customers to achieve first-pass success

• Develop design review checklists and self-assessment tools for OEM customers, supplemented by Astera Labs expert review at critical milestones

• Ensure reference designs and collateral evolve with each silicon generation and incorporate lessons learned from customer engagements

• OEM Relationship Management:

• Build deep, trust-based technical relationships with hardware engineering teams at key OEM customers — becoming their preferred technical partner for Astera Labs silicon integration

• Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources

• Participate in customer roadmap discussions, providing hardware engineering perspective on future silicon requirements, package options, and platform integration considerations

• Capture common customer design challenges, failure modes, and feature requests — feeding these back into reference designs, design guides, evaluation platforms, and silicon requirements

• Support joint development programs with strategic OEM partners — including co-designed products, custom form factors, and platform-specific optimizations

• Silicon Validation Platform Design (SVB/EVB)

• Platform Architecture & Design:

• Own the architecture, design, and delivery of Silicon Validation Boards (SVB) and Evaluation Boards (EVB) for all Astera Labs silicon products — retimers, re-drivers, PCIe/CXL switches, and connectivity ASICs

• Design complex multi-layer PCBs optimized for silicon bring-up, characterization, and performance demonstration — including high-speed channel routing, configurable topology options, comprehensive power delivery, and debug/instrumentation access

• Ensure evaluation platforms provide optimal silicon exercising capability — enabling full characterization of all silicon features, performance modes, and operational corners

• Design platforms that serve dual purposes: internal silicon validation and external customer evaluation/demonstration

• Create modular, scalable platform architectures that can be efficiently adapted across silicon generations with minimal redesign

• Silicon Bring-Up & Characterization Support:

• Partner with silicon design and validation teams to ensure SVB/EVB designs support all required bring-up sequences, test modes, and characterization scenarios

• Support initial silicon bring-up activities on new platforms — providing hardware debug expertise and rapid board-level modifications as needed

• Ensure platform designs enable comprehensive performance characterization — including high-speed link testing, power measurement, thermal characterization, and margin analysis

• Design instrumentation access (probe points, headers, measurement interfaces) that enables efficient silicon debug without compromising signal integrity

• Customer Evaluation Enablement:

• Design evaluation platforms that provide customers a compelling, easy-to-use experience for evaluating Astera Labs silicon in their target applications

• Include customer-relevant interfaces, connectors, and configurations that match real deployment scenarios (OSFP, QSFP-DD, PCIe/CXL slots, network interfaces)

• Develop evaluation platform documentation including user guides, quick-start instructions, test procedures, and application examples

• Support customer evaluation activities — providing technical guidance, interpreting results, and facilitating customer design-in decisions

• Rack-Scale Product Design

• Chassis & System-Level Design:

• Lead the hardware design of rack-scale products including AI chassis-class systems, switch trays, CEM cards, and integrated connectivity platforms

• Own system-level architecture decisions — including backplane/midplane topology, slot configurations, power distribution architecture, cooling strategy, and management interfaces

• Design high-density backplane/midplane PCBs with high-speed interconnect routing supporting 112G/224G PAM4 signaling

• Drive power distribution design for rack-scale systems — including AC/DC conversion, point-of-load regulation, power sequencing, hot-swap protection, and power budgeting

• Design BMC/management subsystems for chassis products — including platform monitoring, thermal management, fault detection, and remote management interfaces

• Mechanical & Thermal Design:

• Direct mechanical engineering for rack-scale products — chassis sheet metal, card cages, cable management, hot-swap mechanisms, rack mounting, and serviceability

• Drive thermal/airflow architecture for chassis systems — including fan tray design, airflow optimization, thermal sensor placement, and thermal throttling strategies

• Evaluate and integrate liquid cooling solutions for high-power-density rack-scale AI infrastructure applications

• Ensure mechanical designs comply with relevant rack standards (OCP, Open19, EIA-310) and customer-specific mechanical requirements

• ODM Collaboration:

• Partner with ODM manufacturers in Asia for chassis and system-level products — providing design specifications, reviewing ODM designs, and driving joint development

• Manage technical ODM relationships for rack-scale products, navigating the differences from traditional CM engagement models

• Conduct design reviews of ODM-proposed solutions, ensuring alignment with Astera Labs' performance, quality, and reliability requirements

• Leverage proximity in Taiwan to maintain close, high-cadence collaboration with ODM engineering teams

• Hardware Validation (Platform & Rack-Scale)

• Define and execute validation strategies for silicon evaluation platforms and rack-scale products — ensuring comprehensive coverage across electrical performance, signal integrity, power delivery, thermal behavior, mechanical integrity, and environmental reliability

• Establish validation methodologies specific to evaluation platforms — including silicon interface verification, channel characterization correlation, power delivery accuracy, and instrumentation validation

• Drive rack-scale product validation including system-level thermal testing, power stress testing, mechanical shock/vibration, EMC/EMI compliance, and safety certification

• Support interoperability testing between rack-scale products and the broader ecosystem of host platforms, NICs, switches, and cables

• Build validation infrastructure in Taiwan that enables local execution of the majority of validation activities without dependency on Santa Clara labs

• Cross-Functional Collaboration

• With Santa Clara HQ:

• Maintain tight alignment with the Senior Director of Hardware Design Engineering and peer engineering leaders on technology roadmap, design standards, and resource priorities

• Collaborate with AEC/SCM hardware design teams to ensure consistency in hardware architecture, design approaches, and validation methodologies

• Engage with Product Management, Sales, Customer Applications Engineering, and Silicon teams to translate customer needs into design requirements and validation plans

• Ensure scalable, repeatable processes for hardware development across Taiwan and Santa Clara, including design reviews, test plans, and documentation

• Establish and maintain governance structures for center execution, budgeting, and metrics to measure impact on OEM engagement, silicon validation success, and rack-scale product readiness

• Stakeholder Alignment:

• Partner with senior leadership in Taiwan and Santa Clara to define strategy, priorities, and resourcing for the hardware engineering center

• Communicate progress, risk, and roadmap updates to executives and key partners

• Represent the company in regional industry events, standards bodies, and customer briefings to promote Astera Labs' hardware capabilities and roadmap

Qualifications

• Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field; advanced degree preferred

• 15+ years of hardware design engineering leadership experience in semiconductor silicon-centric environments, preferably with OEM/ODMs in Asia

• Demonstrated success building and leading multidisciplinary engineering teams in Taiwan or similar regions

• Deep expertise in high-speed PCB design, backplane/midplane architecture, power delivery, thermal management, and signal integrity for 112G/224G PAM4 and related technologies

• Experience designing SVB/EVB platforms, rack-scale systems, and AI chassis-class products

• Strong program management, collaboration, and communication skills with the ability to influence cross-functional teams and external partners

• Proven track record of working with OEM customers, validating silicon platforms, and delivering reference designs and collateral

• Ability to travel regionally to customer sites and partner facilities as needed

• Fluency in English; Mandarin language skills a plus

• Location: Taiwan

• Note: This description is intended to describe the general nature and level of work being performed. It is not intended to be an exhaustive list of responsibilities, duties, or skills required for the position.