About this role
About the Role Skyworks is seeking a verification engineer to verify the digital design intent of SOCs at the block and system levels using systemverilog/UVM. The role involves collaborating with a dedicated team of engineers, engaging early in the verification process to understand requirements, and developing testbenches and tests to achieve coverage closure in a dynamic, fast-paced environment. What You'll Do
- Verify the digital design intent of SOCs at the block and system level using the latest verification practices.
- Engage early in the verification process to understand verification requirements and participate in UVM or SystemVerilog testbench development.
- Create tests to verify the SOC design at system or block level and implement checking mechanisms to ensure coverage closure. What We're Looking For
- 6+ years (BSEE), 4+ years (MSEE), or 3+ years (PhD) of relevant industry experience
- Expertise in developing testbenches using SystemVerilog and UVM
- Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations
- Strong object-oriented programming knowledge using SystemVerilog
- Strong problem-solving and debug skills capable of isolating problems to the block level
- Experience in developing test plans, implementing coverage models, and analyzing results
- Experience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)
- Familiarity with C-code/embedded firmware/debuggers
- Ability to work in a dynamic environment with changing needs and requirements