Technology Layout Engineer

Job title: Technology Layout Engineer

About the Role

The Device Layout and Mask Tooling Engineer will report to the Principal Design Enablement Engineer and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in Cadence for technology development and device modeling, and will support the release of Foundry mask manufacturing requirements for a global design community. Candidate is responsible for developing and supporting internal/external mask tape-out systems, generating and verifying GDS mask data, and MPW/Shuttle releases that impact the development of our BCD technology and the success of our global design community.

What You'll Do

• Generate semiconductor component layouts in Cadence to support semiconductor technology development, process technology transfers, and device modeling.

• Primary interface and support of product design MASK/GDS releases to Foundry.

• Support Allegro product design Business Units with MASK tooling, JDV, and internal tape out system requirements.

• Support Allegro product design Business Units with MASK manufacturing requirements within the Foundry standard systems.

• Develop technology mask tape out workflow standards and documentation.

• Generate technology mask GDS using PDK Booleans for design review and Foundry manufacturing.

• What We're Looking For

• A qualified candidate requires a BSEE with a minimum of 1 year of experience in the industry.

• Basic understanding of EDA design software.

• Working understanding of PDK components to include design rules, mask-gen, models, process parameters, test-chips, and design integration.

• Familiarity with web-based design management tools, documentation, and bug tracking systems.

• Ability to perform in an aggressive learning and problem-solving team environment.

• Proficiency in English is required.

• Nice to Have

• EDA software physical verification tools.

• Knowledge of BCD/BI-CMOS fabrication methods.

• Fundamental understanding of device physics at the transistor design level (cross section, STI, DTI, field plating)

• Compensation & Benefits

• Salary: Not disclosed

• Benefits: Not disclosed

• Note: Salary/benefits not disclosed in the posting.