About this role
Job title: Technical Lead IC Design/Principal - Micro-architecture, RTL Design
About the Role Marvell is seeking a Technical Lead IC Design/Principal specializing in micro-architecture and RTL design for its Optical PHY business unit in Ottawa. In this role, you will guide digital hardware development, contribute to chip design and verification, support back-end teams, and drive timing closure from micro-architecture to customer deployment.
What You'll Do
- High speed data path RTL implementation using Verilog, synthesis and backend resources
- Integrate vendor IP and support
- Full ASIC flow from micro-architecture to customer deployment
- Post-silicon debug and correlation
- Specify and implement digital features of a chip
- Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain analysis and functional verification
- Develop ASIC specification and micro-architecture of signal processing and communications algorithms
- Assist in design automation of various aspects of the CAD EDA flow
- Mentorship of junior team members
What We're Looking For
- Bachelor's degree in Electrical Engineering or related fields and 10+ years of related professional experience
- Experience of entire design cycle from micro-architecture specification definition, Verilog coding, constraint development, synthesis, LEC and timing closure to post-silicon debug and support in lab environment
- Experience with power and latency optimization
- Experience in both RTL development (block and subsystem level) and gate level verification and debug
- Experience with matching DSP block model functionality with RTL, synthesis, static timing analysis and functional verification
- Experience in high speed IEEE compliant DSP physical layer products preferred
- Experience with chip bring up and functional validation of the product in the lab
- Strong system level modeling, debugging and troubleshooting
- Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
- Team player
- Effective communication and presentation skills
- Strong language user in Verilog, System Verilog, Python, Unix Shell
Compensation & Benefits
- Salary range CAD 145,800 - 194,400 per year
- With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.