About this role
Job title: System Modelling Engineer
About the Role As an Analog and Mixed-Signal IP Architect at Intel, you will shape architectures and algorithms for SoC independent IPs, driving innovations in analog/mixed-signal design. You will lead the SerDes PHY System Modeling efforts to support the performance analysis of 224Gbps SerDes IP, focusing on end-to-end PHY modeling across electrical channel, transmitter, and related blocks. This role requires collaboration with design teams to translate specifications into robust, high-performance IP solutions.
What You'll Do
- Lead architecture, modeling, and performance analysis of 224Gbps SerDes IP.
- Drive end-to-end PHY system modeling, including electrical channel, transmitter, receiver interactions, and silicon-aware validation.
- Collaborate with IP and SoC teams to ensure models meet performance and reliability targets.
- Develop, verify, and optimize models for early design exploration and post-silicon validation.
- Provide technical leadership within the SerDes PHY modeling group and mentor peers.
What We're Looking For
- Experience as a SerDes PHY System Modeling Engineer or similar, with focus on analog/mixed-signal IP and high-speed SerDes.
- Strong understanding of analog/mixed-signal IP architectures, PHY/system modeling, channel modeling, and performance analysis.
- Experience with end-to-end PHY modeling, including channel effects, transmitter/receiver interactions, and system-level metrics.
- Familiarity with verification methodologies, modeling tools, and cross-functional collaboration with HW and verification teams.
- Excellent communication and collaboration skills.