About this role
Location: Cambridge, UK Duration: 10 to 12 weeks (Mid-June to September 2027) Paid internship: £30k (undergrad) up to £35k (postgrad)
Please apply by 30th January 2027
About lowRISC
Imagine the innovations we could achieve together if production-ready commercial-grade IP components and engineering systems were available to everyone, for free. At lowRISC, we believe that open-source development can transform the semiconductor industry.
Our Ibex CPU and OpenTitan Root of Trust projects have been taken to production silicon, partnering with world-leading organisations including Google, combining open-source approaches with best practice chip design methodologies.
lowRISC is a non-profit Community Interest Company: with a business model that includes member fees and engineering services we have shown that it is possible to run world-leading projects collaboratively for everyone’s benefit. Originally a spinout from Cambridge University’s Computer Lab, our UK team is based in Cambridge and our Switzerland team is based in Zurich.
The role
We are looking for a Summer Intern with an interest in hardware design to support our engineering teams. This internship offers hands-on exposure to digital design and design verification through open-source projects of commercial grade quality.
You may work on:
- Digital design workflows using SystemVerilog or equivalent
- Developing testbenches and automated verification scripts using UVM or equivalent
- Analysing verification results to improve hardware reliability
- Contributing to open-source repositories and documentation
About you
We are looking for students who:
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Are studying Computer Science, Electronic Engineering or related fields 2nd+ year Bachelor's or part way through a Master's or PhD
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Have experience or interest in digital design or design verification
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Are comfortable with a hardware description language and Python or scripting for verification
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Are curious, proactive, and enjoy collaborative problem solving Bonus skills (not required):
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Familiarity with RISC-V architectures
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Knowledge of UVM / SystemVerilog testbenches
What we offer
- Competitive salary £30k for undergrad, and up to £35k for a postgrad
- Mentorship from engineers leading open-source hardware projects
- Flexible hybrid working environment
- Opportunity to contribute to globally used open-source projects
- Collaborative project based culture