About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Solutions Architect Engineer (AE)
Advanced Packaging, 3D-IC and SI/PI
Location
United States (Remote or Hybrid)
Job Summary
Cadence is seeking a highly motivated and experienced Solutions Application Engineer to support customers developing next-generation advanced packaging solutions, including 2.5D, 3D-IC, chiplet-based architectures, AI/HPC packages, and heterogeneous integration technologies.
The successful candidate will work directly with leading semiconductor companies, OSATs, foundries, and system companies to deploy and optimize Cadence Advanced Package 3D-IC associated design flows. This role combines technical expertise, customer engagement, solution development, and collaboration with R&D to drive customer success and product adoption.
Responsibilities
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Provide technical leadership and application support for Cadence 3D-IC design solutions.
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Assist customers with advanced package architecture, design implementation, and methodology development.
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Develop and demonstrate complete packaging workflows for:
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Organic substrates
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Silicon interposers
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Wafer Level Packaging
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2.5D and 3D-IC integration
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Chiplet-based package architectures
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Support customer evaluations, proof-of-concepts, benchmarks, and production deployments.
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Deliver technical presentations, product demonstrations, workshops, and training sessions.
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Collaborate with sales teams to identify opportunities and provide technical pre-sales support.
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Work closely with R&D to communicate customer requirements, enhancement requests, and new technology needs.
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Support design-signoff methodologies including:
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DRC/LVS
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Connectivity verification
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Electrical rule checking
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Thermal analysis
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Signal Integrity (SI)
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Power Integrity (PI)
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Develop best practices, application notes, reference flows, and customer success methodologies.
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Assist in defining future product direction for advanced packaging, 3D-IC, and chiplet technologies.
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Required Qualifications
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Bachelor’s degree (Masters preferred) in Electrical or Electronics Engineering, or related discipline with
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10+ years of experience in semiconductor packaging, IC packaging, PCB, substrate, or interposer design.
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Strong knowledge of:
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Advanced package design methodologies
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2.5D and 3D-IC integration
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Chiplet-based architectures
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Package manufacturing and assembly processes
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High-speed signal design
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Power delivery networks
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Experience performing package layout, routing, constraint management, and package signoff.
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Solid understanding of package stackups, bump planning, escape routing, and substrate technologies.
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Excellent customer-facing communication and presentation skills.
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Ability to work independently while collaborating across global teams.
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Preferred Qualifications
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Experience with Cadence Integrity 3D-IC Platform.
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Experience with Cadence Sigrity and Clarity 3D Solver.
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Hands-on experience with Cadence Allegro X APD.
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Knowledge of UCIe, HBM, AI accelerator packaging, and heterogeneous integration.
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Experience supporting foundry and OSAT design flows.
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Understanding of semiconductor assembly, reliability, and manufacturing processes.
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Travel Expectations: Approximately 2% to 5% travel, depending on customer demand and business needs.
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The annual salary range for California is $162,400 to $301,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.