SoC PD Lead

The SoC PD Lead role at Advanced Micro Devices is based in Hyderabad, India. You will lead end-to-end physical design for high-performance, low-power SoCs, driving PPA targets, schedule commitments, and cost considerations. You will collaborate with RTL, architecture, CAD, and verification teams, mentor team members, and influence program decisions to deliver robust, scalable designs for next-generation processors and related technologies.

Responsibilities

• Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).
• Establish and drive sign-off criteria and waiver processes.
• Introduce innovative techniques for congestion management, timing optimization, and power integrity.
• Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.
• Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.
• Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.
• Publish risk burndown reports and mitigation plans for tapeout-critical paths.
• Lead technical reviews and provide consultative input to management on design trade-offs.
• Work closely with design teams for area and floorplan refinement, timing targets, pre-Si bug resolution, and PPA sign-off.

Requirements

• 15+ years of experience in the relevant domain.
• Proficient in working with various EDA tools, including Innovus, Fusion Compiler/ICCompiler2, and PrimeTime.
• Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, memory sub-system, fabrics, CPU/GPU coherency, multimedia, I/O subsystems, clocks & resets.
• Excellent communication, management, and presentation skills, with a track record of collaboration across top engineers and senior architects across geographies.
• Bachelor’s or Master’s degree in computer engineering or electrical engineering.