Silicon Design Verification Engineer

Job title: Silicon Design Verification Engineer

About the Role Join HCL Technologies as a Silicon Design Verification Engineer in Sunnyvale, CA. You will help ensure the functional correctness of our next-generation ASICs and SoCs, partnering with architecture and RTL teams to develop verification plans and scalable environments from concept through tape-out. If you are passionate about solving complex hardware challenges and pushing silicon performance, join us.

What You'll Do

• Design, develop, and maintain advanced, scalable verification environments and testbenches using SystemVerilog and UVM.
• Collaborate with RTL designers and hardware architects to define verification strategies and author comprehensive test plans for complex IP blocks and subsystems.
• Write directed and constrained-random tests; triage and debug simulation failures; root-cause and resolve RTL bugs.
• Define and analyze functional and code coverage metrics; drive coverage closure to meet tape-out milestones.
• Develop and maintain automation scripts (Python, Perl, Bash) to streamline simulation, regressions, and reporting flows.
• Participate in the evaluation and adoption of new verification methodologies, formal verification techniques, and EDA tools.
• Assist in running and debugging gate-level simulations (GLS) with and without timing constraints (SDF).

What We're Looking For

• Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience: 3+ years of industry experience in ASIC/SoC pre-silicon verification.
• Hardware Languages: Strong proficiency in SystemVerilog and Verilog.
• Methodologies: Hands-on experience with UVM, OVM, or VMM methodologies.
• Problem Solving: Exceptional analytical and debugging skills with a proven track record of finding complex bugs in RTL designs.
• Scripting: Proficiency in at least one scripting language (Python, Perl, Makefile, or Bash).
• EDA Tools: Experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, or Siemens Questa).

Nice to Have

• Advanced Degree: Master’s degree or Ph.D. in Electrical/Computer Engineering.
• Protocol Knowledge: Familiarity with PCIe, CXL, DDR/LPDDR, Ethernet, AMBA AXI/AHB.
• Formal Verification: Experience using formal verification tools (e.g., JasperGold, VC Formal).
• Emulation/FPGA: Experience with hardware emulation platforms (e.g., Palladium, Zebu) or FPGA prototyping.
• Power Aware Verification: Knowledge of UPF/CPF and experience with power-aware simulation techniques.