About this role
We’re looking for power integrity engineers to ensure that power is delivered and stable at all levels: rack/tray, package, die, core.
Ideal Background:
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Experience with large die, high TDP chip PDN analysis and design
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Experience with advanced node (7nm and lower) chip PDN analysis and design
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Ability to work with package architects to determine best passives design within a given set of constraints
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Ability to work with ASIC and microarchitecture team to hit power integrity goals given manufacturing design constraints
Nice to Have:
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Experience with WSI (wafer-scale integration) systems
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Board and system-level power delivery network analysis and design
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Low voltage die power delivery network analysis and design
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Many voltage domain power delivery network design and analysis
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IVR based design experience