About this role
Job title: Senior Verification Engineer - SystemVerilog/UVM
About the Role Join Skyworks as a Senior Verification Engineer focused on verifying the digital design of SOCs at the block and system levels. You will engage early in the verification process, develop SystemVerilog/UVM testbenches, and create tests to ensure coverage closure in a fast-paced, collaboration-driven environment.
What You'll Do
- Verify the digital design intent of SOCs at block and system levels using the latest verification practices.
- Engage early in the verification process to understand requirements and participate in UVM/SystemVerilog testbench development.
- Create tests to verify SOC designs at system or block level and implement checking mechanisms to ensure coverage closure.
- Develop SystemVerilog/UVM testbenches, implement coverage models, and analyze results.
- Develop test plans, implement coverage models, and analyze results.
- Use scripting languages to support automation (Python, Make, Csh, Bash, Tcl, etc).
- Familiarity with C-code/embedded firmware/debuggers.
- Thrive in a dynamic environment with changing needs and requirements.