Senior Staff- IP RTL Design Engineer

Job title: Senior Staff- IP RTL Design Engineer

About the Role As a Digital IC Design Senior Staff Engineer in Marvell's Central Engineering, you will architect and deliver next-generation IP (UCIe and high-speed interfaces) from micro-architecture through production RTL. You’ll provide technical leadership, collaborate across Architecture and Verification, and mentor a high-performance design team to enable customers in automotive, storage, security, and networking.

What You'll Do

• Architect, design, and implement state-of-the-art RTL for UCIe/HBM and other high-speed IP.
• Own micro-architecture and RTL development for medium to high-complexity digital blocks; drive hands-on RTL coding, synthesis, CDC/RDC analysis, linting, debugging, and bring-up support.
• Partner with Architecture and Verification to define test plans, coverage strategies, and achieve verification closure.
• Participate in design reviews and contribute to IP quality, robustness, and reusability.
• Provide technical leadership by mentoring junior engineers, reviewing designs, and helping build a high-performance design team.

What We're Looking For

• BSEE/MSEE (or equivalent) in Electrical Engineering; 8–14 years of hands-on digital design experience delivering silicon IPs or SoCs.
• Strong domain expertise in high-speed protocols such as UCIe, HBM, Ethernet, DDR, PCIe, USB (direct UCIe/HBM experience strongly preferred).
• Extensive hands-on experience with SystemVerilog/Verilog (VHDL a plus).
• Proven experience with RTL quality and sign-off flows including Lint, CDC/RDC (SpyGlass or equivalent).
• Solid understanding of synthesis, STA, formal checking, and downstream P&R interactions.
• Good grasp of SoC architecture, including processor cores, memories, interconnects, and peripheral interfaces.
• Behavioral & Leadership: demonstrated ability to deliver production-quality designs on aggressive schedules; strong debugging, problem-solving, and cross-functional collaboration skills; ability to take ownership, influence technical direction, and mentor less-experienced engineers.

Nice to Have

• Experience with low-power design techniques and clocking architectures.
• Exposure to post-silicon debug and silicon bring-up.
• Prior experience delivering reusable IPs across multiple products or nodes.

Compensation & Benefits With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.