About this role
About the Role As a Senior Staff Engineer in Digital IC Design, you will own post-RTL design flow for SerDes IPs, including synthesis, timing closure, DFT generation, and ECOs. You will work across block and chip levels and collaborate with analog and digital teams to deliver SerDes IPs for Marvell product lines.
What You'll Do
- Improve the design methodology and flow
- Perform synthesis, timing closure, and DFT support for SerDes IPs ranging from 10Gbps to 224Gbps for various applications
- Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all Marvell product lines
- Provide support to product teams for both pre- and post-silicon
- When needed, execute custom placement and routing for mixed-signal designs
What We're Looking For
- Master’s degree and/or PhD in EE, CS or related fields and 6+ years of experience; strong personal communication and team-working spirit
- Hardworking and motivated to be part of a highly competent design team
- Must have good post-RTL experience including synthesis, timing analysis and physical design; able to perform custom placement and routing for mixed-signal designs; flexible to move between all post-RTL design activities; good understanding of block and top-level physical timing closure
- Proficiency in: logic or physical synthesis using Synopsys or Cadence tools; DFT generation and verification; static timing analysis using Primetime; physical design for 28nm and beyond; strong Perl and Tcl scripting
Nice to Have
- Low power design
- Circuit level or custom design experience
- Floorplanning, clock-tree synthesis and power planning/analysis
- Signal integrity and physical verification
Compensation & Benefits
- Competitive compensation and great benefits, with an environment of shared collaboration, transparency, and inclusivity. For additional information on what it’s like to work at Marvell, visit our Careers page.