Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

Job title: Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

About the Role Marvell is seeking a highly skilled Timing/STA Engineer to drive timing constraints development, STA signoff/margins flows, and timing closure for complex SOCs and blocks. The ideal candidate will collaborate with Architecture, RTL, DFT, and Analog teams and bring experience in deep technology nodes (5nm/4nm) to optimize performance and margin.

What You'll Do

• Develop and validate timing constraints for intricate SoC designs
• Collaborate with Architecture, RTL, DFT, and Analog teams to understand design requirements, analyze timing complexities, and develop consolidated timing modes and constraints for STA signoff
• Own and contribute to STA-related tasks like timing ETs for blocks and SoCs, developing custom scripts to create histograms, STA flow management, etc.
• Perform static timing analysis (STA) using industry-standard tools (e.g. Primetime)
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties
• Resolve or find workarounds for tool issues, independently or with EDA tool vendors
• Conduct post-route timing checks and QoR analysis
• Automate STA-related processes/flow using Tcl or Python
• Create QoR dashboards, histograms for STA runs across all modes
• Ensure compliance with timing signoff checklists and criteria
• Document best practices and lessons learned to drive continuous improvements in future projects

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience
• Minimum of 5 years of industry experience in ASIC timing and STA
• Strong understanding of ASIC design flows, from RTL to GDSII
• Knowledge and hands-on experience with STA methodologies and implementation
• Proficiency in using STA tools, and scripting languages (e.g., Tcl, Perl)
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5
• Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff
• Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure
• Proven track record of delivering successful designs on time and meeting performance, power and area goals
• Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues
• Strong communication and collaboration skills to work effectively within cross-functional teams

Nice to Have

• Experience working on Photonic Fabric ecosystem or related high-bandwidth interconnect technologies

Compensation & Benefits

• Salary range: $135,900 - $201,130 per year (USD)
• Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.