Senior Staff Engineer - AMS IP Verification

Job title: Senior Staff Engineer - AMS IP Verification

About the Role Senior Staff Engineer - AMS IP Verification leads end-to-end verification ownership for complex SerDes/AMS/mixed-signal IPs across 5nm, 3nm, and 2nm nodes. This role drives verification strategy, collaborates across Design, Firmware, and Silicon teams, and mentors engineers to ensure early risk mitigation and high-quality silicon deliverables.

What You'll Do

• Drive end-to-end verification ownership for complex SerDes / AMS / mixed-signal IPs across advanced nodes (5nm, 3nm, 2nm).
• Lead verification of high-speed interfaces including SerDes, PCIe, Ethernet, DDR, D2D, PAM4/PAM2-based designs.
• Define and execute verification plans covering calibration, link training, power modes, analog-digital interaction, and firmware-driven flows.
• Debug and resolve complex issues spanning RTL, AMS models, firmware, VIPs, and system-level behaviors.
• Drive coverage closure, regression stability, and sign-off readiness with high quality standards.
• Own or co-own Gate-Level Simulation (GLS), power-aware verification, CDC/RDC validation, and timing-aware checks.
• Collaborate closely with Design, Architecture, Firmware, and Silicon teams to ensure early alignment and risk mitigation.
• Contribute to verification infrastructure, checkers, automation, and reusable frameworks.
• Mentor junior engineers and act as a technical role model within the team.
• Identify opportunities to improve productivity and quality, including use of automation or AI-assisted verification tools.

What We're Looking For

• 8–12 years of hands-on experience in verification and/or AMS systems.
• Strong expertise in SystemVerilog, UVM, and modern verification methodologies.
• Deep understanding of SerDes / PHY architectures; AMS and mixed-signal verification; Calibration and link training flows; Register models and firmware interaction.
• Experience integrating and using industry VIPs (Synopsys, Cadence, Siemens/Mentor, Avery).
• Proven ability to debug difficult issues across multiple abstraction layers.
• Solid understanding of system-level behavior and trade-offs, not just block-level execution.
• Leadership & Behavioral Expectations:
• Demonstrates strong technical ownership and reliability.
• Leads by example through hands-on execution and disciplined problem solving.
• Communicates technical issues clearly to diverse stakeholders.
• Makes sound decisions under ambiguity with a quality-first mindset.
• Actively supports team growth through mentoring and knowledge sharing.
• Begins to influence technical direction and best practices beyond individual tasks.

Nice to Have

• Experience across multiple technology nodes and IP generations.
• Contributions to verification methodology improvements or reusable infrastructure.
• Exposure to post-silicon debug and correlation.
• Participation in internal tech forums, papers, or conferences (DVCon, VLSI-D, internal reviews).

Compensation & Benefits With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.