About this role
Senior Staff Digital Design Engineer in Marvell's Optical PHY BU, developing cutting-edge optical Ethernet Transceiver ASICs. As part of a digital hardware development team, you will assist in chip design, verification, and back-end timing closure to support cloud-scale connectivity.
Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification. Develop high speed data path and control plane RTL blocks using Verilog, with synthesis and backend resources. Integrate vendor IP and support back-end teams and timing closure. Be well versed with the complete ASIC flow from micro-architecture to customer deployment. Perform post-silicon debug and correlation. Develop ASIC specification and micro-architecture of signal processing and communications algorithms. Assist in design automation of various aspects of the CAD/EDA flow.
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience. 5+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology. Familiarity with the entire design cycle from micro-architecture specification definition, Verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment. Experience with Verilog, SystemVerilog, Python, and Unix Shell. Experience in both RTL development (block and subsystem level) and gate level verification and debug. Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment. Effective communication and presentation skills and a team player.