About this role
About the Role Marvell is seeking a Senior Staff Digital Design Engineer in the Connectivity group to push the limits of data-center and AI infrastructure. You will develop RTL in Verilog/SystemVerilog for digital IP blocks, translate architectures into synthesizable designs, and collaborate with physical design teams to meet timing and power goals.
What You'll Do
- Develop RTL designs using Verilog/SystemVerilog for digital IP blocks and subsystems
- Translate architectural specifications into clean, synthesizable RTL
- Perform linting, CDC and low-power design checks
- Analyze timing, area, and power tradeoffs during design implementation
- Support synthesis and work with physical design teams on timing closure issues
- Debug functional issues discovered during simulation, emulation, FPGA prototyping or silicon bring-up
What We're Looking For
- Bachelor's degree in Computer Science, Electrical Engineering or related fields with 8+ years of experience, or Master’s/PhD with 3+ years
- Independently analyzes and optimizes sub-circuit blocks across process, voltage, temperature
- Responsible engineer for at least one major sub-circuit block from architecture definition to tuning
- Identifies and proposes innovative solutions; participates in root cause investigation and silicon validation
- Mentors and coaches new or less experienced team members
- Knowledge of communication and DSP algorithms preferred
- Verification experience with preference in UVM is a big plus
Nice to Have
- UVM-based verification experience is a plus
Compensation & Benefits
- Base pay range: $135,900 - $201,130 per year (USD)
- Employee stock purchase plan with a 2-year look-back
- Family support programs for work-life balance
- Mental health resources and well-being programs
- Recognition and service awards for contributions and milestones