Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM)

About the Role Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM) will develop and execute verification plans for high-speed memory interfaces as part of Marvell's Center of Excellence within the Custom Compute and Storage (CCS) Business Unit. You will design, verify, and deliver IP subsystems powering Marvell's memory solutions, collaborating across architecture, RTL design, firmware, and silicon validation to ensure performance, interoperability, and testability. This role supports shifting verification left to enable faster time-to-market and first-pass-right silicon across Marvell's SoC products.

What You'll Do

• Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3)
• Build and enhance UVM/SystemVerilog-based verification environments
• Develop test benches, sequences, and checkers for functional and performance validation
• Perform protocol-level verification for memory controllers and PHY interfaces
• Analyze and debug simulation failures, identify root causes, and drive resolution
• Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance
• Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage
• Support emulation/FPGA validation and post-silicon bring-up
• Review design specifications and provide feedback for testability and robustness

What We're Looking For

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
• 5-10 years of experience in ASIC/SoC verification
• Strong knowledge of DDR, LPDDR, or HBM protocols and architecture
• Expertise in SystemVerilog and UVM methodology
• Experience debugging complex verification issues
• Familiarity with industry-standard tools (simulation, waveform debugging, coverage tools)
• Solid understanding of digital design fundamentals

Nice to Have

• Knowledge of JEDEC standards for DDR/LPDDR/HBM
• Experience with assertion-based verification (SVA)
• Exposure to performance modeling and traffic generation
• Exposure to emulation platforms (Palladium, Veloce)
• Scripting skills (Python/Perl/Shell)
• Experience with low-power verification (UPF)

Compensation & Benefits

• Salary range: USD 134,390 - 201,300 per year
• Employee stock purchase plan with a 2-year look back
• Family support programs to balance work and home life
• Mental health resources to prioritize emotional well-being
• Recognition and service awards
• Additional interview process details will be provided during the process