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Senior Staff CAD Engineer, Multi-die 3DIC & Power

Marvell
Santa Clara, CA
On-siteUSD 127,630 / year

About this role

About the Role Senior Staff CAD Engineer at Marvell will be a key CAD member of Marvell Central Engineering, leading development of next-generation Multi-die and Power methodology, CAD flow automation and tool support. You will use your extensive design and CAD knowledge to help define the organization's methodology and workflow.

What You'll Do

  • Develop and maintain next-gen CAD Flows & Methodologies for Multi-die and Power to address the needs of Marvell's various Business Units.
  • Deploy, support, and regress these flows.
  • Collaborate with Infrastructure teams to ensure optimal flow integration within the larger CAD framework.
  • Explore opportunities for agentic AI/ML tools and projects.
  • Drive weekly engagement with external partners and internal customers to track product requirements and EDA tool development.
  • Display strong analytical and problem-solving skills.
  • Participate in industry events and follow industry trends.
  • Demonstrate a constant interest in new ideas and learning, potentially beyond the topics described above.

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
  • 3+ years of hands-on experience in physical design and flow development in an ASIC rtl-to-gds environment.
  • Strong proficiency in TCL and Python scripting for CAD flow development.
  • Comfortable working in an agile environment with constant learning and innovation.
  • Strong verbal and written communication skills.
  • Experience with multi-die topics: 2.5D/3D/3.5D die-stacking, floorplanning, SOIC hybrid bonding.
  • Inter-die extraction, multi-die analysis (IR, STA, thermal).
  • Advanced packaging technologies: CoWoS, EMIB, PIVR, COUPE.
  • Interposer routing for silicon & fanout, SI/PI analysis.
  • Experience with power analysis topics: RTL power estimation & optimization, clock-gating efficiency.
  • ASIC block power, glitch power, UPF.
  • Experience with industry tools: 3DIC Compiler, Integrity 3DIC, Fusion Compiler, InnovusPrimePower, PP-RTL, Empower, Joules, PowerArtist.
  • Ability to work in a fast-paced environment and manage multiple tasks.

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