Senior SoC Compute & Memory Architect

Job title: Senior SoC Compute & Memory Architect

About the Role The CEG NAG (Networking Architecture Group) at Intel is defining the future of high-performance networking silicon. This Senior SoC Compute & Memory Architect will define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms, focusing on performance, scaling, power efficiency, and programmability in hyperscale environments.

What You'll Do

• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache).
• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions).
• Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity.
• Architect system memory subsystems including DDR/LPDDR interfaces, memory controllers and scheduling policies, bandwidth provisioning and scaling.
• Work with Performance architect to define memory access models for compute, network, and accelerator subsystems.
• Balance latency-sensitive control workloads with bandwidth-intensive datapath workloads.
• Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads; design features such as multi-tenant isolation and security boundaries; shared vs isolated memory models.
• Ensure efficient interaction between host, IPU/DPU compute, and offload engines.
• Architect integration between compute, network, storage and accelerator subsystems; optimize data movement to minimize copies, latency, and bandwidth overhead.
• Drive system architecture decisions for balanced SoC performance.
• Define compute and memory strategies for power efficiency and DVFS scalability; memory bandwidth throttling/prioritization; per-subsystem scaling; optimize performance-per-watt at system level.
• Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations; define scaling strategies for core count, frequency, memory bandwidth/capacity, cache topology; ensure backward compatibility across product lines.
• Collaborate with Networking subsystem, SoC fabric/interconnect, firmware/OS/drivers, validation and performance modeling/testing to align architectures and resolve cross-domain tradeoffs.

What We're Looking For

• Minimum Qualifications: Bachelor's degree in Electrical/Computer Engineering or STEM; 10+ years in SoC/CPU/memory subsystem architecture, CPU architecture and cache hierarchies, memory subsystems (DDR/HBM, controllers, QoS), coherent/non-coherent interconnects; system-level performance and PPA tradeoff analysis; ability to drive architecture from concept to silicon.
• Preferred Qualifications: Postgraduate degree; ARM and x86 compute/memory experience including NUMA, cache coherency, or large-scale platform architectures; IPU/SmartNIC or accelerator-centric SoCs experience in cloud/hyperscale; familiarity with PCIe, CXL and memory semantics; track record across multiple generations.
• Behavioral: Architectural vision, influence without authority, systems thinking, decision-making under ambiguity, collaboration, customer-focused mindset, ownership, continuous learning.

Nice to Have

• IPU/SmartNIC or accelerator-centric SoCs experience; cloud/hyperscale deployments; familiarity with PCIe, CXL; track record of multi-generation architecture.

Compensation & Benefits

• Intel invests in our people and offers a complete and competitive package of benefits for employees and their families. See Intel Benefits for details.