About this role
About the Role ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including architecture development, RTL implementation, verification support, and silicon bring-up. Proven expertise in leveraging and deploying AI-generated RTL solutions in production silicon, driving improved design productivity, quality, and time-to-market while ensuring robust functionality and performance. What You'll Do
- IP RTL design for AMDs PCI Express (PCIe) IP used for all next generation server, clients, GPU and Semi-custom products.
- Work closely with IP and system architects to micro-architect cutting edge features.
- Apply low power design techniques to existing logic and maintain overall system performance.
- Focus on timing, LINT and CDC closure to ensure high quality RTL.
- Support verification and debug of the ASIC throughout various stages of the project. What We're Looking For
- Strong working experience in RTL coding using Verilog HDL
- Strong experience with integrating AI-assisted design methodologies into advanced semiconductor development flows from concept through tapeout and post-silicon validation.
- Experience in design with multiple clock domains
- Experience in using lint and CDC tools
- Experience in developing specification
- Understanding of high-speed I/O protocols (PCIe, USB, SATA, Ethernet…) Nice to Have
- Not specified Compensation & Benefits
- Salary: CAD 155,200 – CAD 232,800 per year
- Benefits mentioned: AMD benefits at a glance