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Senior Principal Test Engineer

Marvell
Santa Clara, CA
On-siteUSD 160,200 - 240,000 / year

About this role

Senior Principal Test Engineer within Marvell's Operations. You’ll define the IO Chiplet ATE test strategy, drive cross-functional alignment, and lead development of ATE IP to enable robust qualification and high-volume manufacturing. As the primary technical authority, you will ensure test methodologies, infrastructure, and execution meet performance, quality, and scalability requirements across the product roadmap.

Lead development of ATE test solutions for characterization, production, and wafer sort on the Advantest 93K platform, driving cutting-edge test capability and ensuring products meet the highest quality standards. Design and develop high-speed ATE hardware supporting data rates above 112 Gbps, advancing next-generation test methodologies and enabling future-ready semiconductor products. Create comprehensive test plans and methodologies aligned with stringent product specifications, ensuring robust validation and consistent product performance. Collaborate closely with DFx and Design teams to review testability and test strategies, contributing to improved yield, optimized test methodologies, and cross-functional innovation. Convert design-level test content into ATE-ready test patterns, ensuring seamless transition from simulation to production environments. Drive test flow optimization, reducing test time, eliminating redundant steps, improving yields, and releasing high-quality production test programs in partnership with cross-functional engineering teams.

Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related discipline. Over 12 years of semiconductor test engineering experience, spanning NPI, ATE development, silicon characterization, correlation, and high-volume manufacturing. Proven technical leadership in high-speed and high-power semiconductor test development for AI, networking, and advanced compute products. Deep expertise in ATE test methodologies, silicon process fundamentals, DFT/DFM, high-speed SerDes, and high-power ATE testing. Track record of building scalable ATE architectures and reusable ATE IP for MCM, CPC, and CPO product lines. Strong skill on the Advantest 93K platform. Proficient in Java, C/C++, Perl, Python, and Linux. Strong communicator with excellent teamwork and problem-solving capabilities. Self-driven, adaptable, and effective in fast-moving, dynamic engineering environments.

Base pay range: USD 160,200 - 240,000 per year. Our benefits include an employee stock purchase plan with a 2-year look back, family support programs, robust mental health resources, and recognition/service awards. Details discussed during interview.

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