Senior Principal Memory Architect

About the Role Senior Principal Memory Architect on Marvell’s Custom Cloud Solutions (CCS) Architecture team, driving memory subsystem solutions for next-generation cloud and AI data centers. You will define memory subsystem architecture, develop high-performance HBM/DDR subsystems, and collaborate with customers and internal teams to push memory performance, reliability, and efficiency.

What You'll Do

• Architect high-performance HBM/DDR memory subsystems for Marvell’s custom compute products, including developing specifications, performance models, and product requirements.
• Define and evolve Marvell’s memory controller architecture strategy and roadmap, partnering with customers and internal teams to deliver optimal solutions for next-generation workloads.
• Drive micro-architecture development, design specifications, and verification plans in close collaboration with RTL, physical design, and validation teams.
• Develop system-level models to evaluate and optimize performance (throughput, latency, QoS, power, area) across multiple design options.
• Collaborate cross-functionally with hardware, firmware, and validation organizations to ensure end-to-end product quality, performance, and reliability.
• Lead innovation initiatives around memory subsystem architecture, including ECC, RAS, and reliability improvements for server-class products.
• Represent Marvell in technical discussions with customers and ecosystem partners, influencing industry direction and technical decisions.
• On-site requirement: This role is 100% in-office at our Santa Clara, Irvine or Boise locations five days per week (no remote or hybrid work option).

What We're Looking For

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of relevant experience, or Master’s/PhD with 8+ years in memory architecture or system design.
• Technical Expertise: Deep understanding of DDR/HBM memory subsystem architecture for data center compute, AI, or XPU systems; Proven experience designing or specifying HBM/DDR memory controllers and subsystems; Strong familiarity with JEDEC standards (HBM3/4, DDR4/5, LPDDR5/5X/6) and related memory interface technologies; Experience with system modeling and performance analysis tools; Demonstrated experience developing ECC, RAS, and reliability features for server or high-performance SoC designs.
• Soft Skills: Strong analytical and conceptual thinking with a track record of innovation; Excellent communication skills and the ability to collaborate effectively across global, multi-disciplinary teams; Passion for architecting memory solutions that redefine performance and efficiency in data center computing.

Compensation & Benefits

• Expected Base Pay Range (USD): 191,530 - 286,900 per year.
• Additional Compensation and Benefits: Employee stock purchase plan with a 2-year look back, family support programs, robust mental health resources, and recognition and service awards.