About this role
Senior Principal Engineer - Verification
About the role
Role: Act as the senior technical authority for verification across the organization. Define verification architecture and methodology for the most complex SoCs, solve the hardest technical escalations, and support pre-sales with technical solutioning. Influence comes through leads and principals rather than direct reports.
Experience: 12 to 14 years. Must have 5 or more tapeouts, including multiple complex SoCs, and a record of defining verification methodology at organization level.
Desired Skills:
- Defines the verification architecture for complex SoCs, such as multi-cluster CPUs, coherent interconnects, PCIe, CXL and DDR/HBM subsystems, and chiplet or UCIe-based designs.
- Owns organization-level verification methodology: UVM framework standards, coding guidelines, VIP strategy, regression and coverage infrastructure.
- Expert in advanced techniques: formal verification, emulation and hybrid emulation, Portable Stimulus (PSS), and hardware/software co-verification.
- Evaluates and selects EDA tools, VIPs and flows, and builds strong relationships with EDA vendors.
- Is the escalation point for the hardest bugs, sign-off disputes and verification-closure risks across projects.
- Provides technical solutioning for pre-sales: verification approach, effort models and risk assessment for customer proposals.
- Drives AI/ML-assisted verification initiatives, such as coverage closure, regression triage and test generation.
- Mentors principals and technical leads, and builds technical depth across the verification practice.
- Represents the company in technical discussions with customer architects.
Must-have skills
verification architectureSoC verificationUVM framework
Good-to-have skills
EDA tool evaluationAI/ML verification initiativeschiplet or UCIe experience.
KeenSemi hiring for Senior Principal Engineer - Verification