Senior Principal Engineer - RTL

Job title: Senior Principal Engineer - RTL

About the Role Senior Principal Engineer – RTL/Subsystem Architect at Marvell leads the architecture of end-to-end subsystems, roadmap execution, and integration across product lines. This role focuses on reusable subsystem solutions, guiding standards, and mentoring the team to deliver high-quality SoCs. This role is based in Bangalore, India.

What You'll Do

• Own the future roadmap and execution of the subsystem, standards adoption, and architectural trade-offs.
• Define and drive KPIs (performance, power, security, scalability, compliance) and make technical trade-offs to meet quality.
• Work with third party vendors (Synopsys, ARM) to define customization, requirements and IP roadmap.
• Own and partner on the definition and delivery of subsystem collateral: Architecture specs and PRDs; Integration guides and reference designs; Performance models, benchmarks, and limits; Verification strategy at subsystem level.
• Work with the verification team on reviewing the verification test plans, verification methodologies, full-chip simulation and emulation, performance and power analysis and debugging.
• Work closely with SoC Chief Engineers, Product Architecture, PD, DFT, FW/SW, and System teams.
• Provide mentorship to more junior team members.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 20+ years of related professional experience; Master’s/PhD with 18+ years preferred.
• Experience in creating architectural, micro-architectural, and register specifications.
• Verilog/SystemVerilog RTL coding with SystemVerilog assertions.
• Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up).
• Has worked on complex chips such as network processors, CPUs, GPUs, NOCs, switches, ML SoCs etc.; owning subsystem and block-level architecture and design.
• Strong experience with peripheral interface IPs and protocols including I3C, I2C, SPI/QSPI, UART, GPIO, and USB standards.
• Experience with third-party IP integration from vendors such as Synopsys, Cadence and ARM, including customization and subsystem integration.
• Experience with interconnect fabrics such as Arm and Arteris fabrics, AXI/APB protocols, and NoC architecture.
• Experience with scripting in Perl/Python/Shell and extensive usage of AI agents and tools.

Compensation & Benefits

• Competitive compensation and great benefits; Marvell provides tools and resources to grow and develop with us.
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.