Senior Principal Engineer Analog Design (HBM PHY)

Job title: Senior Principal Engineer Analog Design (HBM PHY)

About the Role Senior Principal Analog Lead to drive the design and delivery of next-generation HBM PHY analog and mixed-signal solutions for AI, HPC, and hyperscale systems. This is a high-impact technical leadership role with ownership of PHY circuit architecture, analog/mixed-signal design, and silicon bring-up, working across digital, system, and packaging domains. You will play a critical role in shaping high-speed interface design at advanced process nodes, pushing the limits of bandwidth, power efficiency, and signal integrity.

What You'll Do

• Own the analog/mixed-signal architecture of HBM PHY, including TX/RX design, clocking, DLL/PLL, reference circuits, training assist circuits, calibration engines, and margining support.
• Lead design of critical high-speed blocks: IO drivers, receivers, equalization, clock distribution, and timing circuits.
• Define and drive: Signal integrity (SI), power integrity (PI), and jitter/noise budgets; partner with logic/RTL architects to co-design training flows, calibration algorithms, and system behavior.
• Drive HBM4 implementation to silicon, while influencing next-generation PHY architectures; Collaborate across Physical Design, Packaging, SI/PI, and system architecture teams.
• Lead design reviews, modeling, and simulation methodologies (including AMS/system-level modeling); Drive post-silicon bring-up, characterization, and debug for high-speed interfaces.
• Engage with memory vendors and ecosystem to ensure interface compliance and interoperability.

What We're Looking For

• Bachelor’s/Master's/PhD in Computer Science, Electrical Engineering or related fields and 15+ years of experience in analog/mixed-signal IC design, with strong focus on high-speed interfaces.
• Proven track record of delivering silicon-proven PHYs or SerDes at advanced nodes.
• Deep expertise in: High-speed IO design (multi-Gbps range): TX/RX circuits, equalization, clocking, jitter optimization.
• Mixed-signal design: DLLs, PLLs, CDR (preferred), voltage references.
• Strong understanding of: SI, PI, jitter, noise, and channel effects; Package and interconnect impacts (2.5D/3D integration, interposers).
• Experience with System-level modeling and co-simulation (AMS / behavioral modeling).
• Proven ability to: Drive architecture and design across cross-functional teams; Debug complex silicon issues and drive root-cause resolution.
• Preferred: Experience with HBMs (HBM3/HBM4) and memory interfaces; background in SerDes, DDR, LPDDR, or GDDR PHY design; exposure to advanced packaging (2.5D/3D, chiplets, interposers); familiarity with equalization techniques, training/DFE concepts, high-speed link design; prior experience working with memory vendors and system teams.

Nice to Have

• HBMs / memory-interface experience (HBM3/HBM4)
• SerDes, DDR, LPDDR, or GDDR PHY design
• 2.5D/3D packaging, chiplets, interposers experience
• Equalization techniques, training/DFE concepts, high-speed link design
• Prior experience working with memory vendors and system teams

Compensation & Benefits

• Competitive compensation and great benefits; environment of shared collaboration, transparency, and inclusivity. We provide tools and resources to grow with us, across AI, HPC, and hyperscale systems.