Senior Principal Digital SoC Architect

Senior Principal Digital SoC Architect

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.

The Opportunity As a Senior Principal Digital SoC Architect, you will be the driving force behind the technical definition, microarchitecture, and execution strategy of Allegro’s next-generation mixed-signal Systems-on-Chip (SoCs). Operating at the pinnacle of our technical career track, you will bridge the gap between high-level market requirements (electric vehicles, ADAS, autonomous systems, and AI data centers) and silicon implementation.

This is a high-visibility, senior technical leadership role where you will define winning, highly integrated architectures, drive corporate IP reuse, steer technology platform roadmaps, and mentor engineering teams globally.

What You Will Do

• SoC Architecture & Definition: Lead the architectural definition and technical specifications (Target Specs) of complex, mixed-signal SoCs. Define CPU/DSP subsystems, bus fabrics, memory maps, power management schemes, and digital/analog interfaces.
• IP Strategy & Reuse: Define and champion the digital IP roadmap (e.g., hardware accelerators, security blocks, communication protocols). Drive global IP reuse strategies to improve design quality and reduce time-to-market.
• Modeling & Feasibility: Develop architectural and transaction-level models to validate performance, latency, and power budgets early in the design cycle.
• Cross-Functional Technical Leadership: Serve as the primary technical bridge between Product Marketing, Analog Design, Digital Design, Physical Design, Verification (DV/MSDV), and Software/Systems teams to ensure flawless top-level integration.
• Functional Safety & Quality: Architect safety-critical features to ensure compliance with automotive functional safety standards (ISO 26262 up to ASIL D) and security protocols (Evita/HSM).
• Technology & Process Roadmapping: Partner with Technology Development to select optimal silicon process nodes (e.g., SG8) and packaging technologies to meet cost, thermal, and performance goals.

What You Will Bring B.S. or M.S. in Electrical or Computer Engineering (Ph.D. preferred) with a deep technical focus. 12+ years of experience in semiconductor digital design, with 5+ years acting as a lead SoC Architect. Deep experience integrating embedded processors (ARM Cortex-M/R, RISC-V), network-on-chip (NoC) interconnects, and memory subsystems (SRAM, Flash, NVM). Mastery of automotive and industrial protocols (CAN-FD, LIN, SPI, I2C, I3C, Ethernet, SENT). Functional Saf