Senior Physical Design Engineer - Subsystem Closure

About the Role Renesas is seeking a Senior Physical Design Engineer to lead MCU/subsystem closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation for complex hierarchical SoCs. You will collaborate with SoC teams on clocking and floorplanning strategies, apply UPF-based power-domain techniques, and develop automation flows to improve design quality. You will mentor subsystem physical-design engineers and work cross-functionally with RTL, STA, power, verification, and back-end teams to ensure smooth closure and mitigate risk. What You'll Do

• Lead MCU/subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.
• Collaborate closely with SoC-level teams to align on clocking and floor planning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.
• Work on the different power domains and implement UPF.
• Apply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with overall SoC clock architecture.
• Develop and refine subsystem closure methodologies and automation flows to improve design quality and efficiency.
• Mentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption.
• Work cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure.
• Proactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions. What We're Looking For
• Education: M.Tech/ B.Tech in Electrical Engineering.
• 7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below).
• Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.
• Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.
• Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.
• Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.
• Deep knowledge of SoC design flows with proven ability to work closely with timing closure, power integrity, clocking, verification.
• Solid understanding of low-power design techniques and power-aware physical implementation.