Senior Mixed-Signal Verification Engineer

Job title: Senior Mixed-Signal Verification Engineer

About the Role Join a dedicated team to verify analog and mixed-signal building blocks for SOCs, focusing on portable, ultra-low power audio applications. You will participate in all aspects of mixed-signal design verification and help develop and implement a verification infrastructure to validate functional and performance requirements.

What You'll Do

• Verify analog and mixed-signal building blocks for SOCs as part of a dedicated team, with emphasis on portable ultra-low-power audio markets.
• Collaborate with design engineers to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements.
• Develop and maintain chip-level performance simulations of mixed-signal SOC designs.
• Create and maintain mixed-signal verification plans based on early system specifications or incomplete design definitions.
• Use Cadence Virtuoso to set up and execute parameterized simulations of analog and SOC designs.
• Produce detailed technical reports and documentation.
• Contribute to flow automation and verification scripting using Python, Matlab, Ocean, Perl, Csh, Make, and related tools.
• Hands-on verification of sub-45nm CMOS SOC designs.
• Experience in power-aware mixed-signal verification.

What We're Looking For

• 8+ years (BSEE) or 8+ years (MSEE) or 3+ years (PhD) of relevant industry experience.
• Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices.
• A keen understanding of modern mixed-signal verification challenges and solutions.
• Solid foundation in network theory, amplifier design and data converters.
• Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs.
• Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs.
• Ability to create and maintain mixed signal verification plans based on early system specifications or incomplete design definitions.
• Competent in the Cadence Virtuoso environment to set up and execute parameterized simulations of analog and SOC designs.
• Experienced in producing detailed technical reports and documentation.
• Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred.
• Experienced in flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc.
• Simulation performance and accuracy trade-offs based on design requirements.
• Experienced in power-aware mixed-signal verification.
• Hands-on verification of sub-45nm CMOS SOC designs.

Nice to Have

• Experience in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics is highly preferred.