Senior Mixed Signal Design Engineer

About the Role Join Intel's cutting-edge mixed-signal IP development team as a Senior Mixed Signal Design Engineer. This role combines analog circuit design expertise with a specialized focus on static timing analysis for next-generation mixed-signal systems. You'll drive timing closure across analog-digital interfaces while supporting verification activities that directly impact Intel's industry-leading products. What You'll Do

• Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces.
• Drive timing optimization and constraint development for complex mixed-signal systems.
• Execute analog circuit design tasks including simulation setup, testbench development, and schematic optimization using Cadence ADE.
• Perform comprehensive mixed-signal verification encompassing analog simulations, behavioral modeling, and timing analysis.
• Analyze simulation results for power, performance, and reliability; debug complex issues in analog testbenches and mixed-signal simulations; root-cause analysis with corrective action implementation.
• Collaborate across disciplines with analog designers, digital architects, RTL teams, and physical design engineers.
• Develop behavioral models to improve simulation accuracy and efficiency; advance verification flows and methodologies; contribute to automation initiatives using scripting and emerging AI technologies. What We're Looking For
• Bachelor's degree in Electrical or Computer Engineering or a STEM-related field with 2+ years of industry experience.
• 2+ years of experience with mixed-signal verification and driving methodology changes/initiatives.
• 2+ years of experience in scripting languages such as Python for automation purposes. Nice to Have
• Postgraduate degree in Electrical or Computer Engineering or a STEM-related field.
• Experience working within mixed-signal systems like SerDes or PLLs.
• Experience with static timing analysis and analog circuit designs.
• Experience with Cadence ADE for running simulations and debugging test benches.
• Experience with script development and automation using AI.
• Experience with mixed-signal design principles, including interfaces between analog and digital domains.
• Experience with analog behavioral modeling (Verilog-A, SystemVerilog, etc.) is a plus.