About this role
Senior IC mask/layout designer for custom analog, RF, and mixed-signal circuits. Lead end-to-end layout development for blocks/IP from concept to tapeout and provide technical guidance on floorplanning, placement, routing, shielding, matching, and layout optimization techniques.
Lead end-to-end layout development for blocks/IP from concept to tapeout. Work closely with junior engineers and contractors for scheduling tasks, guiding floor planning, implementation, reviews, and closure. Collaborate with design engineers and CAD support by maintaining effective communication. Review and approve layouts for quality, DRC/LVS/PEX closure, EM/IR compliance, ESD robustness, and manufacturability. Develop methods to improve efficiency in layout methodology and drive best practices for quality, reliability, and timely outputs.
Bachelor / Master’s Degree with 8-10 years of relevant experience. Strong proficiency in using Cadence Virtuoso XL for layout and Calibre for DRC/LVS/PEX. In‑depth understanding of CMOS IC mask design and verification, with solid knowledge of fabrication, electromigration, IR drop, coupling capacitance, device and signal matching, and Layout‑Dependent Effects (LDE). Self‑driven professional with effective planning and reporting capabilities.