Senior FPGA / RTL Design Engineer - Signal Processing

Job title: Senior FPGA / RTL Design Engineer - Signal Processing

About the Role Silvus is seeking a Senior FPGA Design Engineer - Signal Processing to join the FPGA Engineering team in West Los Angeles, CA. You will participate in all aspects of the R&D lifecycle from concept to field deployment, implementing efficient fixed-point DSP algorithms for Silvus' MIMO wireless networking products.

What You'll Do

• Digital design architecting for wireless communication projects.
• Fixed point design of signal processing blocks in collaboration with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to RF and Software Engineering teams.
• Perform other related duties as assigned.

What We're Looking For

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 6 years of demonstrated experience in FPGA design; OR 4 years of FPGA design experience with a Master of Science degree; OR 2 years of FPGA design experience with a PhD degree.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
• Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Must be U.S. Person (U.S. Citizen or Permanent Resident) due to clients under U.S. federal contracts.
• All employment is contingent upon the successful clearance of a background check and drug test.

Nice to Have

• Master of Science degree in Electrical Engineering (MSEE).
• Experience using MATLAB.
• Experience with communication systems on FPGA or ASIC designs.

Compensation & Benefits

• Compensation: USD 125,000 - 195,000 annually.
• The pay range is a guideline and not a guarantee; actual compensation will vary based on experience and qualifications.