Senior FIP Enablement and Support Engineer

About the Role We are seeking a Senior FIP Enablement and Support Engineer to join the Intel Foundry / DTP Customer Engineering team. The role focuses on Foundational IP QA, packaging, and release processes across Synopsys and Cadence design flows, and owns customer-facing IP release delivery. The successful candidate will collaborate with FIP development teams and ecosystem partners to drive quality, integration, and timely solutions for internal and external customers. What You'll Do

• Package, validate, and release high-volume Foundational IP collateral (Standard Cell libraries, PDK content, GPIOs, PLLs) to IP delivery portals and PLM systems including IPX, UCM, Teamcenter, and FLPR, meeting customer commit dates and quality targets.
• Drive end-to-end release execution for assigned IP families, including QA monitoring, packaging throughput, and adherence to SDLC/SDL certification requirements and Intel IP governance standards.
• Serve as primary technical contact to internal and external customers for technical analysis, debug, and integration support; liaise with FIP development teams to drive resolution of quality and integration issues.
• Coordinate with Technical Program Managers (TPMs) and customer engineering leads on external release communication, customer-facing documentation, and release notes.
• Review IP performance and quality to ensure conformance with desired standards and targets; contribute to QA flows, verification methodology, and release automation.
• Drive continuous improvement in packaging throughput, release tooling, and customer support workflows (e.g., Jira / JSM-based intake and triage).
• Develop customer-facing collateral, including application notes, white papers, integration guides, and other supporting documentation to improve customer experience and reduce support load.
• Mentor junior engineers and contribute to team-wide best practices in IP release and customer support.