About this role
Senior Engineering Lead - DFT
KeenSemi
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About the role
Role: Act as the senior DFT technical authority across the organization. Define DFT architecture and methodology for the most complex SoCs and multi-die designs, solve the hardest silicon test escalations, and support pre-sales with technical solutioning. Influence comes through principals and leads rather than direct reports.
Experience: 12 to 14 years. Must have 8 or more tapeouts, including complex SoCs, and a record of defining DFT methodology at organization level.
Desired Skills:
- Defines DFT for chiplet and 2.5D/3D designs: IEEE 1838, die-to-die interface test, known-good-die strategy and UCIe test.
- Expert in advanced techniques: streaming scan, cell-aware test, in-system test and silicon lifecycle management.
- Owns organization-level DFT standards: architecture templates, flows, sign-off criteria and review checklists.
- Evaluates and selects DFT tools and ATE flows, and builds strong relationships with EDA vendors.
- Is the escalation point for silicon test failures, yield issues and test-cost problems across programs.
- Provides technical solutioning for pre-sales: DFT approach, effort models and risk assessment for customer proposals.
- Mentors principals and DFT leads, and builds DFT depth across the practice. Represents the company in technical discussions with customer architects and test engineering teams.
- Patents, papers or talks (ITC, VTS, DAC) are a plus.
Must-have skills
DFT ArchitectChiplet DFT3D-IC Test
Good-to-have skills
multi-die or chiplet programsEDA tool evaluationpre-sales solutioning
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KeenSemi hiring for Senior Engineering Lead - DFT