Senior Engineer CAD, Physical Verification

Senior Engineer CAD, Physical Verification

Our EDA and Design Enablement team sits at the heart of Micron’s memory development. We build and support the tools, rule decks, and flows that enable world-class CMOS design and physical verification at scale. We work closely with design, layout, and process teams, and we thrive on solving hard technical problems that directly impact product quality and reliability.

As a CAD Engineer, you will play a critical role in enabling robust physical verification across the design ecosystem. You will develop, improve, and support verification tools, rule decks, and flows while partnering closely with engineers across the design and technology stack. This is a hands-on role for someone who enjoys debugging, innovating, and ensuring design correctness and manufacturability.

Join Micron Technology in Guadalajara. Chip in to innovative memory designs impacting HBM, DRAM, and new technologies.

Responsibilities: Develop and improve physical verification tools, rule decks, and methodologies for CMOS designs, including design rule checking, layout versus schematic, design for manufacturability, and programmable electrical rule checking. Apply problem-solving skills to debug and support in-house and commercial EDA verification solutions, improving quality, performance, and efficiency. Collaborate with design, layout, modeling, and process teams to solve physical verification challenges and guide teams on verification requirements and best practices. Evaluate EDA tools and drive innovation in verification methodologies, workflows, and quality while documenting processes and supporting end-user learning. Lead development of AI-assisted and automated workflows, including Copilot-based assistants, agentic AI flows, and rule-aware automation for circuit simulation and verification.

Minimum

Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, or a related field. Proficiency in physical verification or semiconductor CAD engineering, with approximately four or more years of relevant experience in CAD, VLSI, or related semiconductor engineering work. Proficiency in one or more programming or rule-deck languages such as SVRF/TVF for Calibre, Python, or Perl. Experience developing or validating physical verification rule decks and working with Calibre EDA tools and verification flows. Experience with Linux/Unix environments, shell scripting, databases, and version control, combined with effective interpersonal and collaboration skills.

• Preferred

Qualifications

• Understanding of CMOS process fundamentals and layout design rules. Experience developing and debugging DRC/LVS rule decks, including antenna, ESD, latch-up, and reliability checks. Experience with parasitic extraction flows and methodologies. Understanding of physical verification methodologies, flows, and quality metrics.