About this role
About the Role Take lead as the principal architect for Marvell's next-generation switching ASICs, shaping architecture, performance, and silicon leadership for AI, cloud, 5G, and carrier networks. You will define long-term roadmaps, drive architectural vision, and collaborate across hardware, software, packaging, validation, and product teams to bring concepts to silicon and production. This role is onsite in Santa Clara and central to Marvell's strategic technology engine.
What You'll Do
- Lead Architectural Vision and serve as the principal architect for advanced networking ASICs focusing on performance, scale-out/scale-up capabilities, power efficiency, and silicon leadership.
- Define long-term architectural roadmaps for Marvell's next-gen switching platforms serving AI clusters, hyperscale cloud, carrier, and enterprise markets.
- Drive Cross-Functional Systems Thinking by partnering with hardware, software, packaging, validation, and system engineering to deliver coherent, system-level solutions.
- Represent the architecture function in executive-level technical reviews and customer engagements.
- Elevate Engineering Excellence by mentoring senior and junior engineers, helping develop the next generation of Marvell’s technical leaders and fostering a culture of innovation and rigorous design.
What We're Looking For
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field; Master’s or Ph.D. strongly preferred.
- 15+ years of experience in ASIC architecture and design, preferably in networking, switching, or high-performance SoCs; demonstrated leadership in driving complex ASIC or multi-die products from concept through delivery; track record of innovation.
- Deep expertise in system-level architecture for networking ASICs; high-performance switching pipelines, memory subsystems, packet processing, traffic management and buffer management.
- Deep knowledge of Layer 2 / Layer 3 forwarding, QoS, congestion management, and networking protocols; knowledge of Ethernet IO subsystems and SerDes.
- Expertise with behavioral and performance modeling, architectural validation, and system-level tradeoff analysis; strong understanding of system software interaction, control-plane integration, and full-stack implications.
- Exceptional communication skills with the ability to explain complex architectural concepts clearly and persuasively; comfortable operating in a fast-paced, highly innovative environment; proven mentoring capabilities.
Nice to Have
- Patents, publications, or industry-recognized contributions.
- Master’s or Ph.D. strongly preferred (already noted, included for emphasis).
Compensation & Benefits
- Salary range: USD 242,350 – 363,000 per year.
- Employee stock purchase plan with a 2-year look back, family support programs, robust mental health resources, and recognition and service awards.