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Senior Design Verification Engineer

Intel
Santa Clara, California, United States
On-site

About this role

Job title: Senior Design Verification Engineer

About the Role Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team to own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. The role focuses on testbench architecture, test plan development, and coverage closure, working closely with architecture, design, and software teams. It requires strong depth in DV methodologies, protocol verification, and memory subsystem behavior, with breadth in RTL, physical design, and CAD.

What You'll Do

  • Own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff.
  • Drive quality in testbench architecture, test plan development, and coverage closure; collaborate with architecture, design, and software teams.
  • Apply DV methodologies, protocol verification, and memory subsystem behavior.
  • Work across RTL, physical design, and CAD.

What We're Looking For

  • Strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior.
  • Breadth of experience across RTL, physical design, and CAD.
  • Experience with end-to-end verification of IP blocks from planning through signoff.

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