About this role
About the Role Intel Foundry is seeking a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs and ASIC design implementation flows, with a specialized focus on complex multi-voltage domain designs and power-intent verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design service on complex multi-voltage domain designs. What You'll Do
- Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows and digital design signoff methodologies in multi-voltage domain implementation and verification.
- Support and deliver ASIC/digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
- Deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using (VCLP and Conformal LP).
- Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
- Drive customer success through expert guidance and hands-on ASIC design execution.
- Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
- Create application notes, technical design checklists, and deliver training presentations to customers and internal teams.
- Establish and maintain high quality design through implementation and verification methodologies and checklists. What We're Looking For
- US Citizenship required.
- Ability to obtain a US Government Security Clearance.
- Bachelor's degree in Electrical / Computer Engineering, Computer Science, or STEM field.
- 4+ years of experience with advanced CMOS processes (16nm and below).
- 3+ years of experience in ASIC design implementing and verification in low power, multi-voltage domain.
- 3+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting. Nice to Have
- Active US Government Security Clearance with a minimum Secret level.
- Post Graduate degree in Electrical / Computer Engineering, Computer Science, or STEM.
- Experience with state-of-the-art process technology (7nm and below).
- Hands-on experience in physical design implementation and verification for multi-voltage domain in SoC design.
- Experience with EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and SOC level.
- Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
- Customer-facing experience in technical support roles. Compensation & Benefits
- Not specified in the posting. Intel offers a competitive total compensation package.