Senior Analog Design Engineer

About the Role

Join Allegro MicroSystems as a Senior Analog Design Engineer to craft high-performance analog components that power our power management ICs and motor drivers. Operating with a high degree of autonomy, you will drive technical excellence and directly enable Allegro's mission to Innovate with Purpose.

What You'll Do

• Drive the Future: Design at the transistor level to deliver analog power management circuits (e.g. op-amps, comparators, level-shifters, gate drivers, charge pumps) that meet rigorous specifications from chip architects or analog leads.

• Solve Complex Challenges: Use sound judgment and creativity to evaluate design alternatives, performing worst-case simulation techniques to ensure robust performance across all conditions.

• Strategic Negotiation: Partner with Systems Engineers to negotiate specifications, effectively trading off performance versus costs versus development timescales.

• End-to-End Planning: Take ownership of block development, including creating verification plans, providing production test support, and ensuring high-quality, on-time delivery.

• Collaborate Cross-Functionally: Serve as a technical resource for layout, test, and validation teams, understanding the critical impact of your block's performance on the overall chip-level results.

• Lead with Autonomy: Manage small project teams or mentor junior engineers, fostering a culture of technical excellence and collaboration.

• What We're Looking For

• Expert Designer: You hold a Bachelor’s or Master’s degree in Electrical Engineering with 5+ years of relevant experience (or 3+ years with a Master’s) in analog/mixed-signal IC design.

• Technical Specialist: You have comprehensive knowledge of CMOS technology and an understanding of physical design for power management, including parasitics, dielectric, and junction isolation.

• Proven Problem Solver: You have a track record of applying advanced engineering principles to solve wide-ranging assignments with a high degree of independence.

• Tool Mastery: You are a power user of industry-standard EDA tools, specifically the Cadence chip design suite and modern simulation environments.

• Strategic Communicator: You are trained on data up to October 2023.