About this role
IT Services
Belgrade (Serbia)
Hybrid
Job Openning
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Belgrade (Serbia)
Hybrid
- Location: Belgrade, Serbia
- Work mode: Hybrid, 2 days/week in the office
Adaptiq, on behalf of NextSilicon, is looking for a RISC-V Virtualization Engineer.
About NextSilicon:
NextSilicon is reimagining high-performance computing (HPC) and AI through accelerated compute solutions powered by intelligent adaptive algorithms. Its novel software-defined hardware architecture is designed to significantly accelerate supercomputers and advance performance across HPC and AI workloads.
The company is guided by three core values: professionalism, unity, and impact, bringing together engineers who care about quality, collaboration, and meaningful technological progress.
About the Role
You will be the senior individual contributor responsible for the virtualization software component within a wider RISC-V programme. You will lead its hands-on implementation, working with other software engineers, hardware designers and an architect who supports multiple teams. This is a technical leadership role, not a people-management position.
The initial focus is integrating a planned KVM-based approach with developing hardware and establishing that both behave as expected. From there, you will investigate integration issues, benchmark the system and deliver functional and performance improvements. You will also translate virtualization requirements into clear feedback for hardware designers while design decisions remain open.
The role is based in Serbia and requires at least two days per week in an office. Fully remote work is not available for this position.
Key Responsibilities
- Lead the design and implementation of virtualization support for a custom RISC-V platform.
- Own the software component supporting the RISC-V hypervisor extension, working to the specification and documenting any intentional deviations.
- Integrate and adapt existing hypervisor software using the planned KVM-based approach.
- Develop support for guest execution, world-switching and resource isolation.
- Work on two-stage address translation, virtualized I/O and related IOMMU behaviour.
- Validate hardware and software together as the processor design develops.
- Investigate failures across the kernel, hypervisor and hardware, including possible differences in specification interpretation.
- Communicate software requirements and design feedback to hardware engineers.
- Benchmark the integrated system and use the results to guide functional and performance improvements.
- Explain technical decisions, documentation gaps and dependencies to engineers working on the component.
Required Competence and Skills:
- 5+ years of professional software engineering experience, including hands-on experience with virtualization technologies.
- Hands-on experience building or adapting virtualization or hypervisor software for desktop or server systems. This experience need not be from your current role.
- Strong Linux kernel and operating-system internals knowledge, including memory management.
- Strong C and C++ programming skills; most work in this component is expected to be in C.
- Understanding of virtualization fundamentals, including nested or two-stage page tables, virtualized I/O and IOMMU logic.
- Experience diagnosing low-level hardware–software integration issues and working from technical specifications.
- Senior low-level engineering experience and the ability to lead an implementation with unresolved technical questions. The original requirement is 7+ years; candidates with at least five years and directly relevant virtualization experience can be considered.
- Ability to work independently, communicate clearly with hardware and software engineers, and guide colleagues with less virtualization experience.
- A B.Sc. in Electrical Engineering or Computer Science, or equivalent experience.
Nice to Have:
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Hands-on KVM experience. Substantial experience with another hypervisor is also relevant.
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RISC-V experience, particularly with the hypervisor extension. Virtualization experience on x86 or ARM is welcome; prior RISC-V experience is not required.
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Experience with OpenSBI or custom micro-hypervisors.
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Python experience for scripting or internal tools.
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Thank you for your
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interest in us.
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We will reach out soon!
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Thank you for your
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interest in us.
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We will reach out soon!