About this role
The Role
Join the Advanced Architecture, Technology & Verification Group and contribute to FPGA and SoC architecture definition and development with a focus on radiation effects and RAS. The team focuses on the architecture, development, and validation of commercial and radiation tolerant FPGA/ACAP solutions, for the Terrestrial (Telecom, Avionics, Automotive, Datacenter, AI, etc.) and Space markets. You will work as part of an advanced technology and design team with corporate responsibility for Single Event Effects (SEE), radiation effects and RAS mitigation solutions, and competitive technology analysis.
The Person
You have a passion for modern, complex silicon architecture and innovation in the field of radiation effects and RAS for terrestrial and space applications. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
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Apply IC Design and Solid State Physics fundamentals to develop industry-leading solutions for Single Event Effects (SEE), including SEU, SEL, and SEFI, as they apply to FPGAs and space-grade silicon
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Define and develop SEE PDKs (Product Design Kits), test vehicles, and system-level radiation hardening solutions; evaluate test vehicles at the FPGA level
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Contribute to the architecture definition of XQR/Space-grade FPGA and SoC products, including SEE/RAS architectural specifications
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Analyze semiconductor technology scaling and its impact on radiation sensitivity (Moore's Law and More than Moore)
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Build predictive models for next-generation radiation performance, including competitive feature sets, power, and cost trade-offs
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Collaborate closely with Silicon Technology, Advanced Architecture, and Marketing teams
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Preferred Experience
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Experience at a leading semiconductor company in advanced silicon process technologies and architectures
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Deep knowledge of radiation effects (SEU, SEL, SEFI, TID), including underlying physics and impact on semiconductor devices and FPGAs
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Knowledge of FPGA and SoC architecture, implementation, and software tools
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Self-driven, able to set direction and execute independently
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Willingness to travel to worldwide test facilities, and development consortia
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Academic Credentials
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Master's or PhD degree in Electrical Engineering, Applied Physics or equivalent.
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Location: San Jose, CA, US
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This role is not eligible for visa sponsorship.
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LI-CJ3
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LI-Hybrid
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Benefits offered are described: AMD benefits at a glance.
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all the stages of the recruitment and selection process.
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AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.