Quantum Systems Digital Design Engineer II
About this role
Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations. Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning. Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance. Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system‑level design reviews.
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