Principal Subsystem Engineer (Design or DV)

Microsoft’s AISoC silicon team is seeking a Principal Subsystem Engineer (Design or DV) to deliver premium-quality designs once considered impossible. The role focuses on delivering cutting-edge, custom IP and SoC designs capable of high-performance, efficient operation. We are looking for subsystem design and DV leads to guide and implement these efforts.

• Responsibilities

• Technically lead one or more subsystems as a design or DV engineer.

• Collaborate across teams on vertical and horizontal reuse of components.

• Provide technical leadership through mentorship and teamwork.

• Work with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up.

• Possess deep understanding of complex subsystems (such as PCIe, HBM, imaging or control), fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement.

• Hold experience in design or DV domains.

• Design responsibilities include but are not limited to bandwidth, latency, utilization, and power tradeoffs while driving synthesis, timing constraints, floor-planning awareness, and performance tuning. Proficiency in Verilog/SystemVerilog, microarchitecture specification development, RTL coding, integration, and design quality closure (CDC, lint, RDC).

• OR DV expertise includes deep experience in design verification (DV), developing verification strategies and test plans, creating and debugging UVM-based constrained-random testbenches, scoreboards, checkers, and assertions, implementing functional coverage and coverage closure, and applying Agile methodologies for code reviews, sprint execution, and feature deployment.

• Requirements

• Required qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of technical engineering experience; OR a Master’s with 6+ years; OR a Bachelor's with 8+ years; or equivalent experience.

• Other requirements: Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role involves access to export-controlled information and will require proof of citizenship or proof of US residency or other protected status for eligibility assessment. Citizenship verification will be performed with a valid passport where applicable.

• Preferred qualifications: 9+ years of related experience, or combinations of degree and experience as specified. Experience debugging RTL designs, simulation/emulation environments, design quality and static checks, DFT, and handoff to physical design. 8+ years in digital logic design, including microarchitecture specification, RTL coding in Verilog/SystemVerilog, design verification collaboration, and CDC/Lint closure. 8+ years in synthesis, timing constraints, and post-silicon debug for PPA trade-offs. Alternatively, 9+ years of experience in design and integration or DV with a track record delivering high-performance IP/SS/SoC testbenches. Experience with verification across multiple product cycles (definition to silicon) using C++ and UVM. 12+ years of relevant experience and 5+ years in lead roles across cross-functional or cross-time-zone teams. Lead experience for IP or subsystems related to CPUs, VPUs, GPUs, DMA engines, Tensor units, or similar. Experience with AI/ML SoCs and scripting languages such as Python or Perl. Hands-on experience in Formal property verification (DV).