Principal SoC I/O Performance Architect

Job title: Principal SoC I/O Performance Architect

About the Role AMD is seeking a Principal I/O Performance Architect to help define and optimize I/O performance across next-generation SoCs—before the silicon exists and after it returns from the fab. You'll define what 'fast enough' means for bandwidth, latency, and QoS, build the models and experiments that prove it, and use that evidence to steer architecture and design decisions across the company. This is a rare seat at the intersection of architecture, modeling, verification, emulation, firmware/software, and post-silicon analysis. You won't just run tools and report numbers—you'll frame the questions, build the evidence, and drive the decisions. This role offers a unique opportunity to shape the performance strategy of cutting-edge AMD technologies from early concepts through silicon and into platforms.

What You'll Do

• Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems—bandwidth, latency, QoS, ordering, flow control, topology, and congestion.
• Build, extend, and apply performance models to evaluate architectural options early and answer design questions with data-driven recommendations.
• Analyze performance data from models, simulation, emulation, firmware/software tests, traces, and counters, and correlate pre-silicon predictions against RTL, emulation, and post-silicon results.
• Create reusable workloads, synthetic traffic patterns, trace-replay methods, benchmark flows, and KPI-correlation techniques that scale across teams.
• Partner with architecture, design, DV, emulation, firmware, software, validation, and platform teams, communicating tradeoffs clearly in reviews, readouts, and written recommendations.
• Develop automation and AI-assisted workflows to speed sweeps, data reduction, triage, report generation, and model-based exploration.

What We're Looking For

• Familiarity with high-performance I/O, interconnect, memory, and coherency technologies such as PCIe, CXL, IOMMU/SMMU, UALink, Ethernet, InfiniBand, NVLink, UCIe, AXI, CHI, coherent fabrics, or DMA engines.
• Hands-on experience building or using performance models—analytical, event-driven, or transaction-level—with C++, Python, or SystemC/TLM.
• Comfort working with performance data from simulation, emulation, firmware/software tests, traces, counters, benchmarks, and silicon debug tools.
• Demonstrated technical leadership, cross-team influence, and a track record of using performance evidence to shape product or silicon direction.
• ACADEMIC CREDENTIALS: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline—or equivalent practical experience. Candidates with different but relevant backgrounds are encouraged to apply.

Nice to Have

• PREFERRED EXPERIENCE: Familiarity with high-performance I/O technologies and hands-on experience with performance modeling; ability to operate across simulation, emulation, firmware, and software; and a track record of cross-team impact and influence.

Compensation & Benefits

• Salary range: CAD 187,200.00 / Yr to CAD 280,800.00 / Yr.
• Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.