About this role
About the Role Marvell seeks a Principal Product Engineer within the Networking and Compute organization to lead test strategy and productization for AI cloud and data center platforms. This role combines technical leadership with end-to-end ownership of NPI activities and scalable test solutions for hyperscale compute workloads.
What You'll Do
- Drive technical leadership from development through production, ensuring decisions support robust, scalable productization.
- Serve as a primary technical stakeholder during NPI, guiding teams through characterization, debug, qualification, and readiness discussions.
- Align and influence cross-functional engineering teams toward technically sound, full-closure solutions during complex problem-solving efforts.
- Establish and defend test tier architecture across wafer sort, ATE, and SLT, making data-driven tradeoff decisions that balance coverage, escape risk, quality, and cost-of-test.
- Lead ATE-to-SLT correlation efforts and drive structured escape analysis, translating yield and quality signals across test tiers into actionable product and process improvements.
- Evaluate, champion, and help scale emerging SLT technologies, including high-throughput, parallelized test platforms to improve test economics and manufacturing scalability.
- Define, quantify, and defend product quality, reliability, performance, and cost targets based on data and system-level impact.
- Lead technical risk assessments and tradeoff discussions, driving clarity and direction across engineering, operations, and management.
- Represent Product Engineering in customer interactions and internal leadership forums, clearly articulating status, risk, and recommended paths forward.
What We're Looking For
- Expertise in System Level Test platforms and validation work is a must; hands-on experience with SLT board design, DUT fixturing, and socket qualification is strongly preferred.
- Deep understanding of test tier architecture across wafer sort, ATE, and SLT, with the ability to make principled tradeoff decisions on coverage, escape risk, and cost-of-test.
- Demonstrated experience driving ATE-to-SLT correlation, yield learning, and escape containment across test tiers in a volume manufacturing environment.
- Familiarity with emerging high-throughput SLT methodologies — including parallelization strategies, handler and thermal system constraints, and scalable test content development.
- Deep understanding of the end-to-end product lifecycle, with the ability to drive technical decisions that enable scalable productization.
- Strong expertise in structured problem solving and Root Cause Analysis across silicon, test, and manufacturing environments.
- Proven ability to translate complex technical data and analytics into clear, executive-level narratives and recommendations.
- Hands-on experience using ATE for silicon characterization, analysis, and debug; experience with 93K is strongly preferred.
- Solid foundation in applied statistics for product characterization, yield improvement, and quality analysis.
- Working knowledge of data analytics and visualization tools such as JMP and SiliconDash or equivalent platforms.
- Strong planning and prioritization skills across multiple parallel efforts; interest in process automation and workflow optimization is a plus.