About this role
About the Role Lead post-silicon validation of PCIe/SerDes PHY for Marvell storage devices, owning the validation plan and execution. Drive lab bring-up, unit tests, and cross-functional debugging across PHY, PCS, and protocol layers to ensure high-speed signal integrity and reliability. What You'll Do
- Complete responsibility for PCIe/Serdes PHY Validation in post-silicon environment.
- Define, document, execute and report the overall PHY validation/test plan for Marvell storage devices.
- Lead electrical validation of high-speed signal product.
- Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the stack.
- Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
- Analyze and debug issues on Phy protocol of storage interface (PCIe, Ethernet)
- Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
- Leading collaborative technical discussions to drive resolution on technical issues
- Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues.
- Work closely with customers to address design issue and debug failure cases What We're Looking For
- Bachelor’s degree in computer science, Electrical Engineering or related fields and 8+ years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
- Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
- 5+ years experience with High Speed IO testing, debugging and validation
- Strong lab skills with hands on experience, in system bring up, system testing and debug.
- In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
- Strong analytical, problem-solving and communication skills
Preferred/Plus:
- Working knowledge of PCIe and/or SerDes electrical characterization.
- Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
- Working knowledge of board design including schematic design and PCB layout for high speed Serdes Nice to Have
- Optional/preferred qualifications (only if mentioned) Compensation & Benefits
- Salary range: USD 150,680 - 225,700 per year.
- Employee stock purchase plan with a 2-year look back, family support programs, robust mental health resources, and recognition/service awards.
- Additional benefits are provided based on eligibility and role.