Principal PHY SerDes Validation Engineer

Job title: Principal PHY SerDes Validation Engineer

About the Role Marvell seeks a Principal PHY SerDes Validation Engineer to lead post-silicon validation of PCIe and Ethernet PHYs for storage and networking devices. You will own lab bring-up, test planning, and issue resolution across hardware, firmware, and protocol layers to ensure silicon viability for volume production.

What You'll Do

• Complete responsibility for PCIe or Ethernet PHY validation in a post-silicon environment.
• Define, document, execute, and report the overall PHY validation/test plan for Marvell storage devices.
• Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality, extending to the protocol layer of the stack.
• Perform high-speed signal validation and analysis using various test equipment to measure Eye diagram / Jitter / BER.
• Analyze and debug issues on the PHY protocol of high-speed serial interfaces (PCIe or Ethernet).
• Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, and logic/protocol analyzers.
• Lead collaborative technical discussions to drive resolution on technical issues.
• Work with cross-functional teams and external vendors to debug post-silicon and/or customer issues related to PCIe or Ethernet PHY.
• Work closely with customers to address design issues and debug failure cases.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 10+ years of related professional experience, OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related field with 3–5 years of experience.
• Strong understanding of high-speed SERDES, equalization techniques, and PCIe or Ethernet protocols.
• 5+ years of experience with High Speed IO testing, debugging, and validation.
• 5+ years of direct experience in SERDES characterization/design.
• In-depth knowledge of SERDES interfaces using NRZ or PAM4 signaling for PCIe or Ethernet; knowledge of Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.
• In-depth working knowledge of test equipment used for SERDES characterization (scope, BERT, network analyzer, etc.).
• Deep understanding of high-speed electrical signaling principles, differential signaling, and mixed-signal designs.
• Experience in Python for automation framework development, as well as MATLAB.
• Critical thinking, a problem-solving attitude, and ownership of the group’s results.
• Knowledge of SERDES modeling techniques.
• Excellent verbal and written communication skills.

Compensation & Benefits

• Salary range: USD 150,680 – 225,700 per year.
• Additional benefits include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources, and recognition/service awards. More details shared during interviews.