About this role
A Principal Member of Technical Staff (PMTS) in the IODC SoC DFT organization at Advanced Micro Devices in Bangalore, India, will lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs powering next-generation SOCs. This role drives all ATPG execution from architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp, collaborating with RTL, DFT RTL, DFT Verification, Physical Design, Product Engineering Operations, ATE, and Silicon Validation teams to ensure high-quality test content, robust coverage, tester readiness, and successful silicon deployment. The ideal candidate combines deep ATPG and scan methodology expertise with a proven track record of delivering production-quality test solutions for large-scale SoCs, and acts as a technical leader across organizations to influence direction, mentor engineers, and sign off on silicon test readiness.