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Principal IC Digital Design - SoC Design/Micro-architecture

Marvell
Santa Clara, CA
On-siteUSD 158,600 - 237,600 / year

About this role

Job title: Principal IC Digital Design - SoC Design/Micro-architecture

About the Role The Principal Digital IC Design Engineer (DE06T5) is a senior individual contributor responsible for the design, integration, and delivery of complex digital logic for advanced SoC products. This role owns major IP blocks or subsystems and acts as a recognized technical authority within the program or department.

What You'll Do

  • Own RTL design, implementation, and integration of complex blocks or subsystems
  • Define and influence block-level and subsystem-level micro-architecture
  • Develop high-quality, synthesizable RTL using Verilog/SystemVerilog
  • Ensure design correctness through lint, CDC, RDC, and peer reviews
  • Collaborate with verification, validation, Firmware and synthesis/STA, and physical design teams
  • Identify and resolve complex functional, timing, power and integration issues
  • Contribute to digital design methodologies and best practices
  • Mentor and guide junior engineers
  • Participate in design reviews and tape-out readiness

What We're Looking For

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 12+ years of experience in digital IC or SoC RTL design
  • Deep expertise in RTL using system verilog design and micro-architecture
  • Strong understanding of clocking, reset, and power-aware design, SoC architecture, processor cores, memory, peripheral interfaces through hands on prior experience
  • Hands-on experience with lint, CDC, and RDC analysis
  • Proven ownership and track record of block or subsystem delivery on production silicon with aggressive development schedules
  • Strong debugging and problem-solving skills and multi-tasking
  • Experience with ARM AMBA, PCIE, DDR, LPDDR, I2C/SMBus, I3C, USB, UART, QSPI/SPI
  • Hands on experience in interpretive language such as Perl/Python

Nice to Have

  • Experience with large-scale SoC integration
  • Familiarity with low-power design techniques
  • Exposure to synthesis, STA, or physical design flows
  • Experience mentoring engineers or leading technical reviews

Compensation & Benefits

  • Base pay range (USD): 158,600 - 237,600 per year
  • Our total compensation package includes an employee stock purchase plan with a 2-year look back
  • Family support programs to help balance work and home life
  • Robust mental health resources to prioritize emotional well-being
  • Recognition and service awards to celebrate contributions and milestones

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