Principal Engineer - PCIe RTL Design

Job title: Principal Engineer - PCIe RTL Design

About the Role Lead the PCIe/CXL subsystem microarchitecture definition, RTL implementation, and integration. Collaborate with Architecture, Design Verification, Physical Design and firmware teams to translate requirements into robust RTL designs, verify through test plans, and support silicon bring-up and post-silicon debugging. Provide technical leadership and mentorship within the PCIe/CXL design domain.

What You'll Do

• Own and drive PCIe/CXL subsystem microarchitecture definition, RTL implementation, and integration
• Collaborate with Architecture teams to translate requirements into robust RTL designs
• Work with Design Verification teams on test-plan reviews, debug, and coverage closure
• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTLs
• Support silicon bring-up and post-silicon debugging, working with firmware and validation teams
• Drive design quality improvements, coding best practices, and reuse across projects
• Participate in design reviews, milestone reviews, and cross-functional technical discussions
• Mentor junior designers and provide technical leadership within the PCIe/CXL design domain

What We're Looking For

• Master’s or Bachelor’s degree in Electronics/Electrical Engineering with 18+ years of RTL design experience
• End-to-end PCIe/CXL subsystem RTL design execution and sign-off
• Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
• Strong hands-on experience in SystemVerilog / Verilog RTL development
• Expertise in PCIe protocol architecture including link, transaction, and PHY interaction layers
• Deep knowledge of CXL.io, CXL.cache, and CXL.mem architectures
• Experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
• Experience designing high‑performance, low‑latency data paths with ordering, coherency, and error mechanisms
• Solid understanding of Clocking, Resets, CDC/RDC, low‑power techniques, and performance optimization
• Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows
• Proficient in debugging functional and performance issues at subsystem and SoC levels
• Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens
• Proficient in scripting languages such as Tcl / Perl / Python
• Experience with version control systems such as Git, SVN

Compensation & Benefits With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.